Unsupported Verilog Gate Level Primitives - 2023.1 English

Vivado Design Suite User Guide: Synthesis (UG901)
Document ID
UG901
Release Date
2023-06-09
Version
2023.1 English

The following table lists the gate-level primitives that are not supported in Vivado synthesis.

Table 1. Unsupported Primitives
Primitive Status
pulldown and pullup Unsupported
drive strength and delay Ignored
Arrays of primitives Unsupported