Unconstrained Element Types - 2023.1 English

Vivado Design Suite User Guide: Synthesis (UG901)

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2023.1 English

Previously, in VHDL, types and subtypes had to be fully constrained in declaring the type. In VHDL-2008, it is allowed to be unconstrained, and the constraining happens with the objects that are of that type; consequently, types and subtypes are more versatile. For example:

subtype my_type is std_logic_vector;
signal my_reg1 : my_type (3 downto 0);
signal my_reg2 : my_type (4 downto 0);

In previous versions of VHDL, the preceding example was done with 2 subtypes. Now, in VHDL-2008, this can be accomplished with one type. This can even be done for arrays, as shown in the following example:

type my_type is array (natural range <>) of std_logic_vector;
signal : mytype(1 downto 0)(9 downto 0);