USE_DSP Verilog Example - 2023.1 English

USE_DSP Verilog Example - 2023.1 English - UG901

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID

UG901

Release Date

2023-06-09

Version

2023.1 English

(* use_dsp = "yes" *) module test(clk, in1, in2, out1);