Signals - 2023.1 English

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID
UG901
Release Date
2023-06-09
Version
2023.1 English

Declare a VHDL signal in:

  • An architecture declarative part: Use the VHDL signal anywhere within that architecture.
  • A block: Use the VHDL signal within that block.

Assign the VHDL signal with the <= signal assignment operator.

signal sig1 : std_logic;
sig1 <= '1';