Relaxed Return Rules for Function Return Values - 2023.1 English

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID
UG901
Release Date
2023-06-09
Version
2023.1 English

In previous versions of VHDL, the return expression of a function needed be same type as was declared in the functions return type of the function. In VHDL-2008, the rules are relaxed to allow the return expression to be implicitly converted to the return type. For example:

subtype my_type1 is std_logic_vector(9 downto 0);
subtype my_type2 is std_logic_vector(4 downto 0);

function my_function (a,b : my_type2) return my_type1 is
begin
return (a&b);
end function;

Because concatenation is not static, this would return an error or warning in VHDL; however, it is allowed with VHDL-2008.