Referencing Generics in Generic Lists - 2023.1 English

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID
UG901
Release Date
2023-06-09
Version
2023.1 English

VHDL-2008 allows generics to reference other generics, as shown in the following example:

entity my_entity is generic (
gen1 : integer;
gen2 : std_logic_vector(gen1 - 1 downto 0));

In previous versions of VHDL, having the length of gen2 be controlled by gen1 was illegal.