RW_ADDR_COLLISION Verilog Example

RW_ADDR_COLLISION Verilog Example - 2023.1 English

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID

UG901

Release Date

2023-06-09

Version

2023.1 English

(*rw_addr_collision = "yes" *) reg [3:0] my_ram [1023:0];