The RW_ADDR_COLLISION attribute is for
specific types of RAMs. When RAM is a simple dual port, and the read address is
registered, Vivado synthesis infers a block RAM and
sets the write mode to WRITE_FIRST for best timing.
Also, if a design writes to the same address it is reading from, the RAM output is
unpredictable. RW_ADDR_COLLISION overrides this
behavior.
The values for RW_ADDR_COLLISION are:
- auto
- The default behavior as described previously.
- yes
- These inserts bypass logic so that when an address is read from the same time it is written to, the value of the input is seen on the output making the whole array behave as WRITE_FIRST.
- no
- This is when the user does not care about timing or the collision
possibility. In this case, the write mode is set to
NO_CHANGE, resulting in power savings.
RW_ADDR_COLLISION is supported in RTL only.