In the previous example, the signals inside the interface are no longer expressed as
inputs or outputs. Before the interface was added, the port sel
was an
output for bottom1
and an input for bottom2
.
After the interface is added, that is no longer clear. In fact, the Vivado synthesis engine does not issue a warning that these are now
considered bidirectional ports, and in the netlist generated with hierarchy, these are
defined as inouts
. This is not an issue with the
generated logic, but it can be confusing.
To specify the direction, use the modport
keyword, as shown in the
following code snippet:
interface my_int;
logic sel;
logic [9:0] data1, data2, result;
modport b1 (input result, output sel, data1, data2);
modport b2 (input sel, data1, data2, output result);
endinterface : my_int
In the bottom modules, use when declared:
module bottom1 (
my_int.b1 int1,
This correctly associates the inputs and outputs.