MAX_FANOUT VHDL Example - 2023.1 English

Vivado Design Suite User Guide: Synthesis (UG901)
Document ID
UG901
Release Date
2023-06-09
Version
2023.1 English
signal sig1 : std_logic;
attribute max_fanout : integer;
attribute max_fanout of sig1 : signal is 50;
Note: In VHDL, max_fanout is an integer.