Use the KEEP attribute to prevent optimizations where signals
are either optimized or absorbed into logic blocks. This attribute instructs the
synthesis tool to keep the signal it was placed on, and that signal is placed in the
netlist.
For example, if a signal is an output of a 2-bit AND gate, and it drives another AND gate, the KEEP attribute can be used
to prevent that signal from being merged into a larger LUT that encompasses both AND gates.
KEEP is also commonly used with timing
constraints. If there is a timing constraint on a signal that would generally be
optimized, KEEP prevents that and allows the correct
timing rules to be used.
KEEP attribute is
not supported on the port of a module or entity. If you need to keep specific ports, use
the -flatten_hierarchy none setting or put a
DONT_TOUCH on the module or entity itself.KEEP attribute on loadless signals. Synthesis keeps those
signals resulting in issues later in the flow.Examples are:
- When you have a
MAX_FANOUTattribute on one signal and aKEEPattribute on a second signal that is driven by the first; the KEEP attribute on the second signal would not allow fanout replication. - With a
RAM_STYLE="block", when there is aKEEPon the register that would need to become part of the RAM, theKEEPattribute prevents the block RAM from being inferred.
The supported KEEP values are:
- TRUE
- Keeps the signal.
- FALSE
- Allows Vivado synthesis to optimize. The
FALSEvalue does not force the tool to remove the signal. The default value isFALSE.
You can place this attribute on any signal, register, or wire.
KEEP attribute does not force the place and
route to keep the signal. Instead, this is accomplished using the
DONT_TOUCH attribute.