Synthesis is the process of transforming a Register Transfer Level (RTL) specified design into a gate-level representation. AMD Vivado™ synthesis is timing-driven and optimized for memory usage and performance. Vivado synthesis supports a synthesizeable subset of:
- SystemVerilog: IEEE Standard for SystemVerilog-Unified Hardware Design Specification, and Verification Language (IEEE Std 1800-2012)
- Verilog: IEEE Standard for Verilog Hardware Description Language (IEEE Std 1364-2005)
- VHDL: IEEE Standard for VHDL Language (IEEE Std 1076-2002)
- VHDL 2008
- Mixed languages: Vivado supports a mix of VHDL, Verilog, and SystemVerilog.
In most instances, the Vivado tools also support Xilinx design constraints (XDC), which is based on the industry-standard Synopsys design constraints (SDC).
Important:
Vivado synthesis does not support UCF constraints. Migrate UCF
constraints to XDC constraints. For more information, see
ISE to Vivado Design Suite Migration
Guide (UG911).
There are two ways to setup and run synthesis:
- Use Project Mode, selecting options from the Vivado Integrated Design Environment (IDE).
- Use Non-Project Mode, applying Tool Command Language (Tcl) commands or scripts and controlling your own design files.
See the Vivado Design Suite User Guide: Design Flows Overview (UG892) for more information about operation modes. This chapter covers both modes in separate subsections.