In the AMD Vivado™ Design Suite, Vivado synthesis can synthesize attributes of several types. In most cases, these attributes have the same syntax and behavior.
- If Vivado synthesis supports the attribute. It uses the attribute and creates a logic that reflects the used attribute.
- If the specified attribute is not recognized by the tool, the Vivado synthesis passes the attribute and its value to the generated netlist.
It is assumed that a tool later in the flow can use the attribute. For example, the LOC constraint is not used by synthesis. Still, the constraint is used by the Vivado placer and is forwarded by Vivado synthesis.