This chapter describes the supported VHDL language constructs in AMD Vivado™ synthesis and notes any exceptions to support. VHDL compactly describes complicated logic, and lets you:
- Describe the structure of a system: how the system is decomposed into subsystems, and how those subsystems are interconnected.
- Specify the function of a system using familiar language forms.
- Simulate a system design before it is implemented and programmed in hardware.
- Produce a detailed, device-dependent version of a design to be synthesized from a more abstract specification.
For more information, see the IEEE VHDL Language Reference Manual (LRM).