Integer Data Types - 2023.1 English

Vivado Design Suite User Guide: Synthesis (UG901)
Document ID
UG901
Release Date
2023-06-09
Version
2023.1 English

SystemVerilog supports the following integer types:

  • shortint: 2-state 16-bit signed integer
  • int: 2-state 32-bit signed integer
  • longint: 2-state 64-bit signed integer
  • byte: 2-state 8-bit signed integer
  • bit: 2-state, user defined vector size
  • logic: 4-state user defined vector size
  • reg: 4-state user-defined vector size
  • integer: 4-state 32-bit signed integer
  • time: 4-state 64-bit unsigned integer

4-state and 2-state refer to the values that can be assigned to those types, as follows:

  • 2-state allows 0s and 1s.
  • 4-state also allows X and Z states.
X and Z states cannot always be synthesized; therefore, items that are 2-state and 4-state are synthesized in the same way.
CAUTION:
Take care when using 4-state variables; RTL versus simulation mismatches could occur.
  • The types byte, shortint, int, integer, and longint default to signed values.
  • The types bit, reg, and logic default to unsigned values.

See Vivado Design Suite User Guide: Logic Simulation (UG900) for more information about Verilog format for simulation.