Instantiating Verilog in VHDL - 2023.1 English

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID
UG901
Release Date
2023-06-09
Version
2023.1 English

To instantiate a Verilog module in a VHDL design, do the following:

  1. Declare a VHDL component with the same name as the Verilog module to be instantiated. VHDL direct entity instantiation is not supported when instantiating a Verilog module.
  2. Observe case sensitivity.
  3. Instantiate the Verilog component as if you were instantiating a VHDL component.
    • Binding a component to a specific design unit from a specific library by using a VHDL configuration declaration is not supported. Only the default Verilog module binding is supported.
    • The only Verilog construct that can be instantiated in a VHDL design is a Verilog module. No other Verilog constructs are visible to VHDL code.
    • During elaboration, Vivado synthesis treats all components subject to default binding as design units with the same name as the corresponding component name.
    • During binding, Vivado synthesis treats a component name as a VHDL design unit name and searches for it in the logical library work.
      • If Vivado synthesis finds a VHDL design unit, Vivado synthesis binds it.
      • If Vivado synthesis does not find a VHDL design unit, it treats the component name as a Verilog module name and searches for it using a case sensitive search. Vivado synthesis selects and binds the first Verilog module matching the name.
    • Because libraries are unified, a Verilog cell with the same name as a VHDL design unit cannot exist in the same logical library.
    • A newly-compiled cell or unit overrides a previously-compiled cell or unit.