Generate Loop Statements - 2023.1 English

Use a generate-for loop to create one or more instances that can be placed inside a module.

Use the generate-for loop the same way you use a normal Verilog for loop, with the following limitations:

• The generate-for loop index has a genvar variable.
• The assignments in the for loop control refers to the genvar variable.
• The contents of the for loop are enclosed by begin and end statements.
• The begin statement is named with a unique qualifier.