FSM_SAFE_STATE Verilog Example

FSM_SAFE_STATE Verilog Example - 2023.1 English

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID

UG901

Release Date

2023-06-09

Version

2023.1 English

(* fsm_safe_state = "reset_state" *) reg [7:0] my_state;