DSP_FOLDING_FASTCLOCK Verilog Example

DSP_FOLDING_FASTCLOCK Verilog Example - 2023.1 English

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID

UG901

Release Date

2023-06-09

Version

2023.1 English

(* dsp_folding_fastclock = "yes" *) input clk_fast;