Compilation Units - 2023.1 English

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID
UG901
Release Date
2023-06-09
Version
2023.1 English

System Verilog supports both single file and multiple file compilation through use of Compilation units.

A compilation unit is a collection of one or more SV source files compiled together. Every compilation unit is associated with single library. The compilation unit scope is a scope that is local to a global compilation unit, the scope has all the declarations that lie outside of any other design scope. Generally functions, tasks, parameter, nets, variables, and user defined types declared outside the module, interface, package or program come under the compilation unit scope.

For example, consider the following design.

In Tcl mode

read_verilog -lib lib1 {test1.sv }
read_verilog -lib lib2 {test2.sv }
read_verilog test3.sv

Or

IDE

Figure 1. IDE

In the previous case, if test1.sv has declarations in the compilation unit scope such as params, typedefs and so on, like

Parameter P1 =2; // Parameter declared out of module scope
Module test1 (<port list>)
...
...
endmodule

and read the files as mentioned previously. Compiler unit scope starts with reading file test1.sv under lib1, but while reading test2.sv with lib2 would be illegal because compilation unit should be associated with single library. This can be addressed by following ways:

In Tcl mode, putting all the files in a single library.

read_verilog -lib lib1 {test1.sv}
read_verilog -lib lib1 {test2.sv}
read_verilog test3.sv

or not declaring libraries at all

read_verilog {test1.sv }
read_verilog {test2.sv}
read_verilog test3.sv

or (single file compilation unit mode)

read_verilog -lib lib1 {test1.sv}
read_verilog -lib lib2 {test2.sv}
read_verilog test3.sv
synth_design -top <top_name> -sfcu
Figure 2. Settings