Combinatorial Processes - 2023.1 English

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID
UG901
Release Date
2023-06-09
Version
2023.1 English

You can model VHDL combinatorial logic with a process, which explicitly assigns signals a new value every time the process is executed.

Important: No signals should implicitly retain its current value, and a process can contain local variables.