Blocking Procedural Assignment Syntax Example Two (Alternate) - 2023.1 English

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID
UG901
Release Date
2023-06-09
Version
2023.1 English
if (in1) out = 1'b0;
else out = in2;

This assignment blocks the current process from continuing to execute additional statements at the same time, and is used mainly in simulation.

For more information regarding Verilog format for Vivado simulation, see Vivado Design Suite User Guide: Logic Simulation (UG900).