Behavioral Verilog Module Declaration Example One

Behavioral Verilog Module Declaration Example One - 2023.1 English

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID

UG901

Release Date

2023-06-09

Version

2023.1 English

module example (A, B, O);
input A, B;
output O;
assign O = A & B;
endmodule