ASYNC_REG Verilog Example - 2023.1 English

ASYNC_REG Verilog Example - 2023.1 English - UG901

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID

UG901

Release Date

2023-06-09

Version

2023.1 English

(* ASYNC_REG = "TRUE" *) reg [2:0] sync_regs;