Vivado Design Suite User Guide: Synthesis (UG901) - 2023.1 English - Details using AMD Vivado™ synthesis to transform an RTL design into a gate-level netlist for implementation in an AMD FPGA, using SystemVerilog, Verilog, and VHDL. Describes the use of Vivado synthesis in Project and Non-Project Modes, employing multiple synthesis strategies and design constraints. - UG901

Document ID

UG901

Release Date

2023-06-09

Version

2023.1 English