Pre-RTL I/O Planning - 2023.1 English

Vivado Design Suite User Guide: I/O and Clock Planning (UG899)

Document ID
UG899
Release Date
2023-05-16
Version
2023.1 English

You can create an empty I/O planning project to enable early device exploration and initial I/O port assignment before the design source files are available. With this method, you do not have RTL source files or a netlist, and you are working on initial I/O planning and board-level integration. This enables PCB and FPGA designers to agree on an early pinout definition, which can eliminate iterations related to device pinout changes later in the design cycle. Using the I/O planning project, you can:

  • Import device and I/O port assignments from the PCB designer or create I/O ports manually.
  • Export device and I/O port assignments to hand off to the PCB designer or for use later in the design process.
  • Migrate an I/O planning project to an RTL project when the port definitions and pin assignments are resolved.
  • Create a Verilog or VHDL module definition for the top-level of the design based on your port definitions.

    When you complete the port assignments in the I/O planning project, you can migrate the project to an RTL project and create the Verilog or VHDL module definition for the top-level of the design. This allows you to use the agreed upon I/O plan as the start of your RTL design. For more information, see Migrating an I/O Planning Project to an RTL Project.

    Note: For information on creating an I/O planning project, see section I/O Planning Projects in the Vivado Design Suite User Guide: System-Level Design Entry (UG895). For information on importing pin assignments defined by the PCB designer or from another Vivado Design Suite project, see Defining and Configuring I/O Ports.