Adding IP from the IP Catalog - 2023.1 English

Vivado Design Suite User Guide: System-Level Design Entry (UG895)

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2023.1 English
Tip: By default, the IP catalog only displays IP cores that are compatible with, or supported by the target part (or board) for the current project. You can change the default setting to show all IP in the catalog by deselecting the Hide toolbar button in the Vivado IP catalog.

You can add IP cores from the AMD IP catalog, into your design hierarchy, by selecting IP from the catalog, and customizing the IP for your design. Customization involves modifying parameters or features of the IP core, and adding the IP source files into your design project. The IP catalog also lists the interfaces that are available for use in IP integrator.

  1. To begin, select the IP Catalog in the Flow Navigator of the Vivado IDE. This opens the catalog as shown below.

    For information on filtering the IP cores displayed in the IP catalog, and other details of working with the catalog, see this link in Vivado Design Suite User Guide: Designing with IP (UG896).

    Select an IP from the IP catalog and customize the IP for use in your design using one of the following methods:

    • From the IP catalog, select the IP and select the Customize IP command from the right-click menu.
    • Double-click the selected IP to open the Customize IP dialog box for the selected IP core.

    The Customize IP dialog box shows the various parameters and options available to customize the IP. The contents of the Customize IP dialog box varies, depending on the specific IP you select, and can include one or more tabs in which to enter values.

    When you select OK to close the Customize IP dialog box, and confirm the settings you have specified, the IP source files, including the HDL definition of the IP module, are added to your design project and displayed in the IP Sources tab of the Sources window.

    With the IP added to your design, you must generate any files required to support the IP in your design, such as the instantiation template, XDC constraints, and simulation sources. These files are referred to collectively as output products. See Generating Output Products for IP Cores for more information.