write_inferred_xdc - 2023.1 English

Vivado Design Suite Tcl Command Reference Guide (UG835)

Document ID
UG835
Release Date
2023-05-16
Version
2023.1 English

Write file with inferred xdc timing constraints

Syntax

write_inferred_xdc [‑force] [‑all] [‑append] [‑async_clocks]
    [‑all_async_reg] [‑clock_groups] [‑clocks] [‑excl_clocks] [‑exceptions]
    [‑io_constraints] [‑merge_existing_constraints] [‑name <arg>] [‑quiet]
    [‑verbose] [<file>]

Usage

Name Description
[-force] Overwrite existing file.
[-all] Generate all constraints except missing clocks which are generated with the -clocks option
[-append] Append the constraints to file, don't overwrite the constraints file
[-async_clocks] Find asynchronous clock groups
[-all_async_reg] Find the missing ASYNC_REG property for safe and unsafe Clock Domain Crossing
[-clock_groups] Find asynchronous and exclusive clock groups, equivalent to options -async_clocks -excl_clocks
[-clocks] Find missing clock definitions
[-excl_clocks] Find logically and physically exclusive clock groups
[-exceptions] Find missing exceptions
[-io_constraints] Find missing input and output delays
[-merge_existing_constraints] Add existing user defined constraints to the generated constraints
[-name] Start constraints wizard in a GUI panel with this name. Do other command options can be combined with -name.
[-quiet] Ignore command errors
[-verbose] Suspend message limits during command execution
[<file>] Filename to write constraints into

Categories

FileIO, Timing

Description

You can use the write_inferred_xdc to find constraints that should be defined in the open synthesized or implemented design. Write timing constraints that are automatically generated by the Vivado® timing engine, rather than defined in an existing XDC file and added to the design.

Run write_inferred_xdc -clocks first to define suggested clock and generated clock constraints. The suggested clock constraints will be defined with a period of 1 ns. You can edit the recommended constraints to create clocks and generated clocks with the required clock period to meet the needs of your design.

You can add the edited constraints file into the design using read_xdc, or add_files, and update_timing.

You may need to run the write_inferred_xdc command multiple times, using various options like -clock_groups or -async_clocks, to capture all inferred timing constraints from the fully clocked design. You can use an iterative process of writing and sourcing the inferred clocked constraints, and then writing and sourcing additional constraint files to capture all inferred constraints. See the example below for more information.

This command returns a transcript of the process when successful, or returns an error if it fails.

Arguments

-force - (Optional) Overwrite the specified output file if it already exists.

-all - (Optional) Write all XDC constraints for the current design, except missing clocks. The missing clocks can be separately obtained using the -clocks option.

-append - (Optional) Append the output of the command to the specified file rather than overwriting it.

Note: The -append option can only be used with the -file option.

-async_clocks - (Optional) Find asynchronous clock groups that should be defined using the set_clock_groups -asynchronous constraint.

-all_async_reg - (Optional) Find missing ASYNC_REG properties for safe and unsafe Clock Domain Crossing.

-clock_groups - (Optional) Find asynchronous and exclusive clock groups, equivalent to specifying both the -async_clocks and -excl_clocks options in the same command.

-clocks - (Optional) Find missing clock and generated clock definitions that should be defined by the create_clock and create_generated_clock constraints.

Tip: This is the default report generated by the write_inferred_xdc command when no other constraint options are specified.

-excl_clocks - (Optional) Find physically and logically exclusive clock groups that should be defined using the set_clock_groups -physically_exclusive constraint or the set_clock_groups -logically_exclusive constraint.

-exceptions - (Optional) Find missing timing exceptions that should be defined by timing constraints such as set_false_path or set_multicycle_path that change the default assumptions for timing paths in the design.

-io_constraints <arg> - (Optional) Find missing I/O constraints such as set_input_delay, and set_output_delay.

-merge_existing_constraints - (Optional) This option reports existing user-defined constraints matching the type of inferred constraints currently being reported by the write_inferred_xdc command.

Tip: The existing constraints are written to the specified file as comments so that the inferred constraints file can be read into the Vivado Design Suite using read_xdc without conflicting with existing constraints.

-name <arg> - (Optional) Specifies the name of the results set to return the reported constraints to when running in the Vivado IDE.

-quiet - (Optional) Execute the command quietly, returning no messages from the command. The command also returns TCL_OK regardless of any errors encountered during execution.
Note: Any errors encountered on the command-line, while launching the command, will be returned. Only errors occurring inside the command will be trapped.
-verbose - (Optional) Temporarily override any message limits and return all messages from this command.
Note: Message limits can be defined with the set_msg_config command.

<file> - (Required) The filename to write the inferred XDC constraints to. You should specify a file extension as part of the file name, as the write_inferred_xdc command will not provide one.

Note: If the path is not specified as part of the file name, the file will be written into the current working directory, or the directory from which the tool was launched.

Examples

The following example writes the inferred clock constraints in the current design:

write_inferred_xdc -clocks C:/Data/design1_inferred_clocks.xdc

The write_inferred_xdc command may need to be run multiple times to capture all the inferred constraints, as is shown in this example:

write_inferred_xdc -clocks clocks.xdc
source clocks.xdc
write_inferred_xdc -all all.xdc
source all.xdc
write_inferred_xdc -async_clocks async.xdc
source async.xdc