set_system_jitter - 2023.1 English

Vivado Design Suite Tcl Command Reference Guide (UG835)

Document ID
Release Date
2023.1 English

Set system jitter


set_system_jitter [‑quiet] [‑verbose] <system_jitter>




Name Description
[-quiet] Ignore command errors
[-verbose] Suspend message limits during command execution
<system_jitter> System jitter: Value >= 0




Sets the system jitter specified in nanoseconds (ns) for all clocks in the design, including primary and generated clocks. System jitter is used to account for excessive noise that affects all the clocks within the FPGA, like power supply noise and board noise. The default system jitter is technology-dependent and is predefined for each Xilinx® FPGA family based on device characterization with several power supplies under all supported operating conditions.

System Jitter is a component of the Total System Jitter (Tsj) used in the calculation of clock uncertainty for a path. It is due to the maximum noise (in time) that can be seen on the Vccint rail due to simultaneous switching of internal nodes, cross talk and other phenomenon that can impact timing on any path in the design.

Important: The jitter calculated by Xilinx takes into consideration the uncertainty introduced by the clocking resources, the input jitter and the system jitter. Using the set_system_jitter command overrides the default system jitter value calculated by Xilinx, and is not recommended.

The System Jitter and the Input Jitter are random jitters which typically follow a Gaussian distribution and are added in a quadratic manner to represent the worst case combination. When the Input Jitter is null, the Total System Jitter (Tsj) for an internal register-to-register path has the following equation:

  • Tsj = √(SourceClockSystemJitter2 + DestinationClockSystemJitter2)

For example, when using the default value for system jitter of 50ps:

  • Tsj = √(0.0502 + 0.0502) = 0.071ns = 71ps

The set_system_jitter command applies to all the clocks in the design. Use the set_input_jitter command to specify additional jitter for a specific primary clock.

Tip: SYSTEM_JITTER is reported as a property of clocks, although it applies to all clocks in the design. INPUT_JITTER is also a property of primary clocks. These properties can be returned by the get_property or report_property commands.

This command returns nothing if successful, or returns an error if it fails.


-quiet - (Optional) Execute the command quietly, returning no messages from the command. The command also returns TCL_OK regardless of any errors encountered during execution.
Note: Any errors encountered on the command-line, while launching the command, will be returned. Only errors occurring inside the command will be trapped.
-verbose - (Optional) Temporarily override any message limits and return all messages from this command.
Note: Message limits can be defined with the set_msg_config command.

<system_jitter> - (Required) Specifies the system jitter specified in nanoseconds (ns) to be applied system-wide. The jitter specified by the set_system_jitter command overwrites the default value.


This example defines the primary clock, sysClk, and specifies a system wide jitter of 0.1 ns:

create_clock -period 10 -name sysClk [get_ports sysClk]
set_system_jitter 0.1

The following example defines a primary clock, sysClk, and a generated clock, sysClkDiv2, that is a divide by two version of the primary clock. A system jitter of 0.2 ns is specified that applies to all the clocks in the design. An additional input jitter of 0.09 ns is specified on only the primary clock:

create_clock -period 10 -name sysClk [get_ports sysClk]
create_generated_clock  -name sysClkDiv2 -source [get_ports sysClk] \
   -divide_by 2 [get_pins clkgen/sysClkDiv/Q]
set_system_jitter 0.2
set_input_jitter sysClk 0.09

The follow example defines two primary clocks, sysClk and procClk. A system jitter of 0.2 ns is defined for all the clocks in the system. An additional input jitter of 0.05 ns is specified for the clock procClk:

create_clock -period 10 -name sysClk [get_ports sysClk]
create_clock -period 25 -name procClk [get_ports procClk]
set_system_jitter 0.2
set_input_jitter procClk 0.05