set_input_delay - 2023.1 English

Vivado Design Suite Tcl Command Reference Guide (UG835)

Document ID
UG835
Release Date
2023-05-16
Version
2023.1 English

Set input delay on ports

Syntax

set_input_delay [‑clock <args>] [‑reference_pin <args>] [‑clock_fall]
    [‑rise] [‑fall] [‑max] [‑min] [‑add_delay] [‑network_latency_included]
    [‑source_latency_included] [‑quiet] [‑verbose] <delay> <objects>

Usage

Name Description
[-clock] Relative clock
[-reference_pin] Relative pin or port
[-clock_fall] Delay is relative to falling edge of clock
[-rise] Specifies rising delay
[-fall] Specifies falling delay
[-max] Specifies maximum delay
[-min] Specifies minimum delay
[-add_delay] Don't remove existing input delay
[-network_latency_included] Specifies network latency of clock already included
[-source_latency_included] Specifies source latency of clock already included
[-quiet] Ignore command errors
[-verbose] Suspend message limits during command execution
<delay> Delay value
<objects> List of ports

Categories

SDC, XDC

Description

Tip: The XDC > Timing Constraints language templates and the Timing Constraints Wizard in the Vivado® IDE offer timing diagrams and additional details around defining specific timing constraints. You can refer to these sources for additional information.

Specifies the external system-level path delay on a primary input port relative to a clock edge at the interface of the design. The input delay value is specified in nanoseconds (ns), and can be positive or negative, depending on the clock and data relative phase at the interface of the device.

To accurately model the system-level timing of your Xilinx® FPGA design, you must assign timing delays for objects external to the FPGA onto the primary input or output ports in your design. These delays are defined by the set_input_delay and set_output_delay commands.

Important: If the input port also has a set_max_delay constraint assigned, the specified input delay value is considered part of the max_delay computation. That is, the input delay consumes a portion of the max delay on the timing path that includes the input port.

This command returns nothing if successful, or returns an error if it fails.

Arguments

-clock <arg> - (Optional) Indicates that the input delay is relative to the specified clock. By default the rising edge is used. However the -clock_fall argument can be used to indicate that the falling edge should be used instead.

-reference_pin <arg> - (Optional) Specifies that the delay is relative to the active edge of a clock appearing on the specified pin or port rather than a clock.

-clock_fall - (Optional) Specifies that the delay is relative to a falling edge of the clock rather than rising edge.

-rise - (Optional) Specifies the input delay applies to rising transitions on the specified ports. The default is to apply the delay for both rising and falling transitions.

-fall - (Optional) Specifies the input delay applied to falling transitions on the specified ports. The default is to apply the delay for both rising and falling transitions.

-max - (Optional) Indicates the input delay specified is only used when calculating the maximum (longest) path delays.

-min - (Optional) Indicates the input delay specified is only used when calculating the minimum (shortest) path delays.

-add_delay - (Optional) Add the specified delay constraint to the port, to coexist with any other set_input_delay constraints already defined on the port. The default behavior is to replace the existing delays.

-network_latency_included - (Optional) Indicates that the clock network latency of the reference clock is included in the delay value. The Vivado timing engine considers the clock edge reaching the capture flop after the clock latencies unless the specified input or output delay value includes the source latency or network latency.

-source_latency_included - (Optional) Indicates that the source latency of the relative clock is included in the specified delay value.

-quiet - (Optional) Execute the command quietly, returning no messages from the command. The command also returns TCL_OK regardless of any errors encountered during execution.
Note: Any errors encountered on the command-line, while launching the command, will be returned. Only errors occurring inside the command will be trapped.
-verbose - (Optional) Temporarily override any message limits and return all messages from this command.
Note: Message limits can be defined with the set_msg_config command.

<delay> - (Required) The input delay specified as nanoseconds (ns) to apply to the specified ports. Valid values are floating point numbers, with a default value of 0.

<objects> - (Required) The list of ports to which the delay value will be assigned.

Examples

The following example specifies the input delay on port DIN. The input delay is 3 and is relative to the rising edge of clock clk1:

set_input_delay -clock clk1 3 DIN

The following example specifies the input delay on port DIN. The input delay is 2 and is relative to the falling edge of the clock clk1:

set_input_delay -clock_fall -clock clk1 2 DIN

The following example specifies the input delay on port reset. The input delay is 2 and is relative to the rising edge of the clock that appears on the pin wbClk_IBUF_BUFG_inst/O, originating from the clock wbClk:

set_input_delay -clock wbClk 2 -reference_pin \
   [get_pin wbClk_IBUF_BUFG_inst/O] reset

This example creates a clock named clk_ddr, and defines input delay constraints from data launched by both rising and falling edges of the clock outside the device to the data input of the internal flip-flop that is sensitive to both rising and falling clock edges:

create_clock -name clk_ddr -period 6 [get_ports DDR_CLK_IN]
set_input_delay -clock clk_ddr -max 2.1 [get_ports DDR_IN]
set_input_delay -clock clk_ddr -max 1.9 [get_ports DDR_IN] -clock_fall -add_delay
set_input_delay -clock clk_ddr -min 0.9 [get_ports DDR_IN]
set_input_delay -clock clk_ddr -min 1.1 [get_ports DDR_IN] -clock_fall -add_delay
Note: The use of the -add_delay option allows the new min and max delay constraints to exist alongside the first delays on the same port.

The following example specifies the input delay on all non clock input ports of the design. Although all_inputs returns all ports of the design, including clock ports, set_input_delay will skip setting input delays on the clock ports. The input delay is 1 relative to the rising edge of the clock wbClk:

set_input_delay -clock wbClk 1 [all_inputs]

The following example sets an input delay of 4 relative to the rising edge of the clock wbClk on the ports reset and wbDataForInput:

set_input_delay -clock wbClk 4 [list reset wbDataForInput]