refresh_hw_pcie - 2023.1 English

Vivado Design Suite Tcl Command Reference Guide (UG835)

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2023.1 English

Refresh the PCIe core properties, by reading from HW.


refresh_hw_pcie [‑quiet] [‑verbose] <hw_pcie>


Name Description
[-quiet] Ignore command errors
[-verbose] Suspend message limits during command execution
<hw_pcie> Hardware PCIe object




Refresh for the Peripheral Component Interconnect Express (PCIe) debug core object, hw_pcie, defined on the current hardware device.

The customizable LogiCORE IP PCIe core for Xilinx® ACAPs is designed for evaluating and monitoring the PCIe Link Training and Status State Machine (LTSSM) running on the Gigabit Transceivers (GTs). In the Vivado® Hardware Manager, Versal PCIe soft cores implemented in the design, are represented as hw_pcie objects. You can use these PCIe debug cores to solve a range of debug and validation problems; from viewing the PCIe link information to the LTSSM state transition diagram.

This command reads data from the PCIe debug core and updates the relevant properties in the hw_pcie object.


-quiet - (Optional) Execute the command quietly, returning no messages from the command. The command also returns TCL_OK regardless of any errors encountered during execution.
Note: Any errors encountered on the command-line, while launching the command, will be returned. Only errors occurring inside the command will be trapped.
-verbose - (Optional) Temporarily override any message limits and return all messages from this command.
Note: Message limits can be defined with the set_msg_config command.

<hw_pcie> - (Required) List of HW PCIe objects


The following example refreshes the PCIe core at index 0

refresh_hw_pcie [lindex [get_hw_pcies] 0]