create_generated_clock - 2023.1 English

Vivado Design Suite Tcl Command Reference Guide (UG835)

Document ID
UG835
Release Date
2023-05-16
Version
2023.1 English

Create a generated clock object

Syntax

create_generated_clock [‑name <arg>] [‑source <args>] [‑edges <args>]
    [‑divide_by <arg>] [‑multiply_by <arg>] [‑combinational]
    [‑duty_cycle <arg>] [‑invert] [‑edge_shift <args>] [‑add]
    [‑master_clock <args>] [‑quiet] [‑verbose] <objects>

Returns

New clock object.

Usage

Name Description
[-name] Generated clock name
[-source] Master clock source object pin/port
[-edges] Edge Specification
[-divide_by] Period division factor: Value >= 1 Default: 1
[-multiply_by] Period multiplication factor: Value >= 1 Default: 1
[-combinational] Create a divide_by 1 clock through combinational logic
[-duty_cycle] Duty cycle of clock period: Range: 0.0 to 100.0 Default: 50.0
[-invert] Invert the signal
[-edge_shift] Edge shift specification
[-add] Add to the existing clock in source_objects
[-master_clock] Use this clock if multiple clocks present at master pin
[-quiet] Ignore command errors
[-verbose] Suspend message limits during command execution
<objects> List of clock source ports, pins, or nets

Categories

SDC, XDC

Description

Tip: The XDC > Timing Constraints language templates and the Timing Constraints Wizard in the Vivado® IDE offer timing diagrams and additional details around defining specific timing constraints. You can refer to these sources for additional information.

Generate a new clock object from an existing physical clock object in the design.

Clocks can be added to a design in one of three ways:

  • Primary physical or virtual clocks defined with the create_clock command.
  • Derived clocks defined with the create_generated_clock command generated from a primary physical clock.
  • Derived clocks automatically generated by the Vivado Design Suite when a clock propagates through an MMCM/PLL/BUFR.

You can also use the create_generated_clock command to change the name of clocks that the Vivado tool has auto-derived from an MMCM/PLL/BUFR. In this case, a new clock is not created, but an existing clock defined on the specified source object is renamed to the provided name. This requires -name and <object> to be specified, and supports the use of -source and/or -master_clock to further identify the clock to rename when multiple clocks exist on the source object. Refer to the Vivado Design Suite User Guide: Using Constraints (UG903) for more information on renaming auto-derived clocks.

Important: You cannot rename a clock that is already in use by other constraints at the time of renaming. You must rename the clock prior to any other appearance or use of the clock in an XDC file.

This command returns the name of the clock object that is created, or returns an error if it fails.

Arguments

-name <arg> - (Optional) The name of the generated clock to create on the specified object, or the name to assign to an existing clock on the specified object. If no name is specified, the generated clock will be given the name of the <object> it is assigned to. If assigned to multiple <objects>, the name will be the first object in the list.

-source <arg> - (Optional) The pin or port of the master clock from which to derive the generated clock. The master clock must be a previously defined physical clock, not a virtual clock; but can be a primary clock or another generated clock. If the source pin or port currently has multiple clocks defined, the -master_clock option must be used to identify which clock on the source is to be used to define the generated clock.

-edges <arg> - (Optional) Specifies the edges of the master clock to use in defining transitions on the generated clock. Specify transitions on the generated clock in a sequence of 1, 2, 3, by referencing the appropriate edge count from the master clock in numerical order, counting from the first edge. The sequence of transitions on the generated clock defines the period and duty cycle of the clock: position 1 is the first rising edge of the generated clock, position 2 is the first falling edge of the generated clock and so defines the duty cycle, position 3 is the second rising edge of the generated clock and so defines the clock period. Enclose multiple edge numbers in braces {}. See the example below for specifying edge numbers.

-divide_by <arg> - (Optional) Divide the frequency of the master clock by the specified value to establish the frequency of the generated clock object. The value specified must be >= 1, and must be specified as an integer.

-multiply_by <arg> - (Optional) Multiply the frequency of the master clock by the specified value to establish the frequency of the generated clock object. The value specified must be >= 1, and must be specified as an integer. The default is 1.

-combinational - (Optional) Calculate the generated clock latency by tracing delays through only the combinational paths between the source pin of the generated clock and the source pin of the master clock. By default the tool computes the latency for the generated clock by tracing both sequential and combinational paths.

-duty_cycle <arg> - (Optional) The duty cycle of the generated clock defined as a percentage of the new clock period when used with the -multiply_by argument. The value is specified as a percentage from 0.0 to 100. The default value is 50.0.

-invert - (Optional) Create a generated clock with the phase inverted from the master clock.

-edge_shift <arg> - (Optional) Shift the edges of the generated clock by the specified values relative to the master clock. See the example below for specifying edge shift.

-add - (Optional) Define multiple clocks on the same source for simultaneous analysis with different clock waveforms. Use -name to specify the new clock to add. If you do not specify this option, the create_clock command will automatically assign a name and will overwrite any existing clock of the same name.

Note: -master_clock and -name options must be specified with -add.

-master_clock <arg> - (Optional) If there are multiple clocks found on the source pin or port, the specified clock object is the one to use as the master for the generated clock object.

Note: -add and -name options must be specified with -master_clock.
-quiet - (Optional) Execute the command quietly, returning no messages from the command. The command also returns TCL_OK regardless of any errors encountered during execution.
Note: Any errors encountered on the command-line, while launching the command, will be returned. Only errors occurring inside the command will be trapped.
-verbose - (Optional) Temporarily override any message limits and return all messages from this command.
Note: Message limits can be defined with the set_msg_config command.

<objects> - (Required) The pin or port objects to which the generated clock should be assigned. If the specified objects already have a clock defined, use the -add option to add the new generated clock and not overwrite any existing clocks on the object.

Examples

The following example defines a generated clock that is divided from the master clock found on the specified CLK pin. Since -name is not specified, the generated clock is assigned the same name as the pin it is assigned to:

create_generated_clock -divide_by 2 -source \
   [get_pins clkgen/cpuClk] [get_nets fftEngine/CLK]

The following example defines a generated clock named CLK1 from the specified source clock, specifying the edges of the master clock to use as transition points for the generated clock, with edges shifted by the specified amount. In this example, the -edges option indicates that the second edge of the source clock is the first rising edge of the generated clock, the third edge of the source clock is the first falling edge of the generated clock, and the eighth edge of the source clock is the second rising edge of the generated clock. These values determine the period of the generated clock as the time from edge 2 to edge 8 of the source clock, and the duty cycle as the percentage of the period between edge 2 and edge 3 of the source clock. In addition, each edge of the generated clock is shifted by the specified amount:

create_generated_clock -name CLK1 -source CMB/CLKIN -edges {2 3 8} \
-edge_shift {0 -1.0 -2.0} CMB/CLKOUT
Note: The waveform pattern of the generated clock is repeated based on the transitions defined by the -edges argument.

This example creates two generated clocks from the output of a MUX, using -master_clock to identify which clock to use, using -add to assign the generated clocks to the Q pin of a flip flop, and using -name to define a name for the generated clock, since the object it is assigned to has multiple clocks assigned:

create_generated_clock -source [get_pins muxOut] -master_clock M_CLKA \
-divide_by 2 -add -name gen_CLKA [get_pins flop_Q]
create_generated_clock -source [get_pins muxOut] -master_clock M_CLKB \
-divide_by 2 -add -name gen_CLKB [get_pins flop_Q]

The following example renames the automatically named clock that is derived by the Vivado Design Suite on the MMCM clock output:

create_generated_clock -name CLK_DIV2 [get_pins mmcm/CLKOUT1]