A bit-lane definition determines which bits in a CPU bus access are assigned to particular block RAMs. Each definition takes the form of MemType with Placement data, followed by the bit numbers and AddressRange the bit lane occupies. The syntax is, as follows:
<BitLane MemType=”RAMB32” Placement=”X2Y19”>
<DataWidth MSB=”31” LSB=”16”/>
<AddressRange Begin=”0” End=”2047”/>
<Parity ON=”false” NumBits=”0”/>
</BitLane>Typically, the bit numbers are given in the following order:
<DataWidth MSB=bit_num LSB=bit_num>If the order is reversed to have the least significant bit (LSB) first and the most significant bit (MSB) second, UpdateMEM bit-reverses the bit-lane value before placing it into the block RAM.
As with BusBlocks, the order in which bit-lanes are defined is important. But in
the case of bit-lanes, the order infers which part of BusBlock CPU access a bit-lane occupies. The
first bit-lane defined is inferred to be the most significant bit-lane value, and the last defined
is the least significant bit-lane value. In the following figure, the most significant bit-lane is
BRAM7, and the least significant bit-lane is BRAM0. As seen in example Figure 1 layout, this corresponds with the
order in which the Bit Lanes are defined.
When UpdateMEM inputs data, it takes data from data input files in Bit Lane sized
chunks, from the most right value first to the left most. For example, if the first 64 bits of input
data are 0xB47DDE02826A8419 then the value 0xB4 is the first value
to be set into a block RAM.
Given the Bit Lane order, BRAM7 is set to 0xB4, BRAM6 to 0x7D, and so on until BRAM0 is set to 0x19. This process repeats for each successive Bus Block access block RAM set until the memory space is filled or until the input data is exhausted. The following figure expands the first Bus Block to illustrate this process.
The Bit Lane definitions must match the hardware configuration. If the MMI is defined differently from the way the hardware actually works, the data retrieved from the memory components will be incorrect.
Bit Lane definitions also have some optional syntax, depending on what device type keyword is used in the Address Block definition.
When specifying block RAM cells, the physical row and column location within the FPGA device can be indicated. Following are examples of the physical row and column location:
Placement=”X3Y5”Use the Placement= keyword to assign the corresponding block RAM to a specific resource location in the FPGA device. In this case the block RAM is placed at column 3 and row 5 in the FPGA device.
In addition to using correct syntax for bit-lane and BusBlock definitions, you must take into account the following limitations:
- While the examples in this document use only byte-wide data widths for clarity, the same principles apply to any data width for which a block RAM is configured.
- There cannot be any gaps or overlaps in bit-lane numbering. All bit-lanes in an Address Block must be the same number of bits wide.
- The bit-lane widths are valid for the memory device specified by the device type keyword.
- The amount of byte storage occupied by the Bit Lane block RAMs in a BusBlock
must equal the range of addresses inferred by the start and end addresses for a BusBlock.
- All BusBlocks must be the same number of bytes in size.
- A block RAM instance name can be specified only once.
- A BusBlock must contain one or more valid bit-lane definitions.
- An address Block must contain one or more valid BusBlock definitions.
UpdateMEM checks for all these conditions and transmits an error message if it detects a violation.