Transceivers - 2023.1 English

Power Design Manager User Guide (UG1556)

Document ID
UG1556
Release Date
2023-05-16
Version
2023.1 English

GTY, GTY, and GTM are serial transceivers used for serial data transmission in AMD Versal™ adaptive SoC.

In Versal devices, hard IP block selection is dissociated from GT page to Hard IP Blocks pages. Hard IPs should be configured on Hard IP Blocks page in Versal adaptive SoC.

GTY

The Versal adaptive SoC GTY supports continuous data rate from 1.2 Gbps to 32.75 Gbps. Versal GTY page has few differences when compared to previous device families.

The following Versal device clock sources are different:

LCPLL
LC-tank based VCO for low jitter, supports maximum data rates.
RPLL
Ring-oscillator based, slightly lower power, lower data rates.
Note: It is recommended to use Add GTY interface or Manage IP to enter a GTY configuration for a desired protocol, so that all columns are correctly specified. Versal devices include the following changes to the GTY configuration.
Table 1. Transceiver Power Estimation (GTY)
Source UltraScale+ Device Versal Device
LCPLL QPLL (shared to four channels) LCPLL (shared to two channels)
Debug Eyescan Not currently supported
Ring PLL CPLL RPLL
Ethernet MAC CMAC MRMAC

GTYP

GTYP is a superset of GTY in every way, including IP and pin compatibility. It is an upgraded version of GTY that supports PCIe® Gen5. For more information on GTYP, see Versal Adaptive SoC GTY and GTYP Transceivers Architecture Manual (AM002).

GTM

GTM is a high performance transceiver that supports PAM4 and NRZ modulations. Versal adaptive SoC GTM supports non-continuous data rates between 9.5 Gbps to 116 Gbps. For more information, see Versal Adaptive SoC GTM Transceivers Architecture Manual (AM017).