Programmable Logic Power - 2023.1 English

Power Design Manager User Guide (UG1556)

Document ID
UG1556
Release Date
2023-05-16
Version
2023.1 English

The Programmable Logic consists of the following components:

  • Logic
  • Block RAM
  • UltraRAM
  • DSP
  • I/O
  • Transceivers

You should define the clocks first so that they can be associated with the resource entries on the other pages. Organization of data entries is important for accurate power estimation. This lets you avoid underestimation resulting from parts of the design being overlooked and to avoid overestimation by duplication by inadvertently entering the same resources more than once. Use the following common strategy for estimating the power of large designs.

  • Enter rows of resources corresponding to each major hierarchical design block, using the block name or instance name as a base name for the row.
  • Enter at least one row of resources for each clock within each hierarchical block.
  • For logic on clock domain crossings, group the logic with its associated clock.
  • Within each clock domain, use multiple rows for resources with different toggle rates.