Power Supply Design - 2023.1 English

Power Design Manager User Guide (UG1556)

Document ID
UG1556
Release Date
2023-05-16
Version
2023.1 English

The power supply design table displays all of the required information to correctly design the power supply and power decoupling network based on the current estimation.

Figure 1. Power Supply Design
Power Rail Group (Read Only)
Displays the required power rail groups based on the device selection and the power rail consolidation.
Schematic Name
Allows you to add your own schematic name reference for each of the power rail groups. This is added to the exported XML file when using with the power vendors or the schematic checklist.
Power Domain/Sequence (Read Only)
Displays the power domain that the regulator is part of and its position in the power on and off sequence.
Tip: The power off sequence is the reverse of the power on sequence. PDM provides all sequencing information for the PMC and other domains based on the power rail consolidation options selected.
Figure 2. Power Domain and Sequence
Voltage
Allows you to alter the voltage of the power rail. Any changes here impact all the power supplies connected to it in the power supply table.
Tip: It is recommended to keep the voltage at the TYP value, because this means that there is a balanced positive and negative range for the power supply design to cover AC ripple and DC tolerance. The AC ripple and DC tolerance values only apply when the voltage is set to TYP, if you adjust the voltage then the AC ripple and DC tolerance requirements need to be recalculated to ensure the power rail stays within the allowed range.
AC Ripple
Shows the allowed AC ripple on each of the Power Rail groupings.
DC Tolerance
Shows the allowed DC tolerance of the regulator output
Dynamic (A)
Sum of the dynamic current of the Versal adaptive SoC rails supplied by the power rail based on the current estimation.
Step Current (A)
Sum of the step loads of the Versal adaptive SoC rails supplied by the power rail based on the current estimation.
Total (A)
Total current requirement for the power rail, sum of the Versal adaptive SoC rails supplied by the power rail. If the Power ON current is greater than the operating current, then the PoC requirement is shown.
Power Delivery Supply Current (A)
Allows you to enter the power delivery current specification for each rail for validation. When you enter the current for each rail, it is validated against the current power estimation. For most accurate results, ensure that the estimation is up to date. If possible, an import from the Report_Power is used and validated.
Power Delivery Margin
Allows you to validate your selected power delivery when entering the current for each power rail group. PDM validates and indicates the power delivery solution margin. Characterization level is used to ensure margin is added to the dynamic requirements. The calculation is, Static Requirement + (Dynamic Requirement + Char Level).

Decoupling Capacitors Table

The decoupling capacitor table indicates the required decoupling based on the current estimation and the step load entered for VCCINT. The table lists six types of capacitors. The following is the size and self resonant frequency of each capacitor:
330µF-1210
Typical self resonant frequency is 0.3 MHz.
100µF-0805
Typical self resonant frequency is 0.5 MHz.
47µF-0603
Typical self resonant frequency is 0.8 MHz.
22µF-0603
Required for the transceivers. Typical self resonant frequency is 1.0 MHz.
10µF-0402
Typical self resonant frequency is 2 MHz.
1.0µF-0201
Typical self resonant frequency is 10 MHz.
Tip: It is recommended a PDN simulation is done to validate the decoupling capacitors quantity and placement is based on the completed PCB design.