Power Estimation - 2023.1 English

Power Design Manager User Guide (UG1556)

Document ID
UG1556
Release Date
2023-05-16
Version
2023.1 English

This section describes NoC, DDRMC, and HBMMC settings.

Figure 1. Power Estimation

The NoC page is divided in tables of NoC & DDRC (also HBM for HBM enabled devices). Migrate to each page for configuration and power details.

Table 1. NoC Property Description
Property Description
NoC Clock Clock frequency of NoC operation in MHz. You can edit it based on the allowed range, speed grade, and voltage selected. Fmax of the NoC clock is 1080 MHz in a -3H device.
Data Path Select the data path between Master and Slave for which NoC power is being estimated. This entry has the drop-down list of around 17 valid data paths between different masters and slaves available in Versal devices like PS, PL, AI Engine, PMC, CPM, and DDRMC.
Bandwidth This field specifies the read and write bandwidth requirement for that particular data path. The unit is MBps and the maximum bandwidth supported is 19200 MBps.
Transaction Size Specify the transaction size of the traffic data for read and write interface being transferred through NoC. This size is in bytes and the maximum size supported for write and read transaction is 64 bytes.
Switches

This field is auto-populated based on your input and this represents the average number of NoC programmable switches required in the given data path.

When a .xpe is imported, this field reports actual number of NoC switches used in each corresponding path.

Clock Buffers This field is auto-populated based on your data path input. It determines the average number of Clock Buffers used for a path. It adds up per path and maximizes to total available for the device. NoC clock power is directly proportional to the number of clock buffers used.