PL Power management dashboard enables early "What-if" power saving analysis like Clock Gating, Frequency Scaling, Logic Gating, and so on. This helps you become aware of some of the Power Management features to explore during the early phase of the design power estimation.
All the clocks in the design is automatically added in Power management dashboard.
The following Power management modes are introduced in the PDM tool.
- Clock Gating
In this mode, the PL clocks are gated the same way as a zero frequency clock for Logic, BRAM, URAM and DSP.
- Frequency Scaling
This mode is used to determine the power savings when the frequency is scaled. You need to enter the absolute frequency after scaling on which circuit is operating.
- % of Gated Logic
This mode determines what will be the logic power if a particular % of logic at reset state. This can be set only when clock gating is disabled, because when clock gating is enabled, logic power is 0.
Note: Any change in the Power management page does not reflect in any other corresponding pages like Clock, Logic.
- Summary of Savings
- You can use this table to determine what will be power saving in the total design, based on modes selected for each clock. As multiple clocks can have multiple power management modes.