PL Power Management - 2023.1 English

Power Design Manager User Guide (UG1556)

Document ID
Release Date
2023.1 English

PL Power management dashboard enables early "What-if" power saving analysis like Clock Gating, Frequency Scaling, Logic Gating, and so on. This helps you become aware of some of the Power Management features to explore during the early phase of the design power estimation.

All the clocks in the design is automatically added in Power management dashboard.

Figure 1. Power Management

The following Power management modes are introduced in the PDM tool.

  1. Clock Gating

    In this mode, the PL clocks are gated the same way as a zero frequency clock for Logic, BRAM, URAM and DSP.

  2. Frequency Scaling

    This mode is used to determine the power savings when the frequency is scaled. You need to enter the absolute frequency after scaling on which circuit is operating.

  3. % of Gated Logic

    This mode determines what will be the logic power if a particular % of logic at reset state. This can be set only when clock gating is disabled, because when clock gating is enabled, logic power is 0.

    Note: Any change in the Power management page does not reflect in any other corresponding pages like Clock, Logic.
Summary of Savings
You can use this table to determine what will be power saving in the total design, based on modes selected for each clock. As multiple clocks can have multiple power management modes.
Current Design
Represents total power of the design without any power management
Only Clock Gating
This shows the total design power and power savings only due to clock gating.
Only Frequency scaling
This shows the total design power and power savings only due to frequency scaling of the clocks whichever selected.
Only Logic Gating
This shows total design power and power savings as result of % Logic held at reset.
Clock Domain Power
This table allows you to select the power management modes based on the clocks.
Potential Savings
This table shows the power savings per clock domain. It has 3 different columns that represent how power is saved per Power Management mode per clock.