PCIE - 2023.1 English

Power Design Manager User Guide (UG1556)

Document ID
UG1556
Release Date
2023-05-16
Version
2023.1 English

AMD Versal™ adaptive SoC devices have a dedicated PCIe® core in the MAC column, denoted as PCIe. It is a standalone Gen4x8 core without an embedded DMA engine, and supports Gen1, Gen2, Gen3 and Gen4 line rates. The link widths are x1, x2, x4, x8 or x16 link widths (x16 configuration supported only for speeds Gen1-3). The combination of PCIe® block, block RAMs/UltraRAMs, GTs, and fabric clocking implements three layers of the PCI Express protocol– the physical layer, data link layer and transaction layer. For more information, see Versal Adaptive SoC Integrated Block for PCI Express LogiCORE IP Product Guide (PG343).

Versal Premium devices support PCIe5, which can support up to Gen5x4 data rates.

PCIe/PCIe5 hard block can be populated from the Create GTY/GTYP Wizard from PCIe page or GTY/GTYP page.

Figure 1. PCIe View
Figure 2. PCIe Configuration