NoC Power Estimation Flow - 2023.1 English

Power Design Manager User Guide (UG1556)

Document ID
UG1556
Release Date
2023-05-16
Version
2023.1 English

PDM allows two ways to estimate NoC power from AMD Vivado™ :

Manual Entry

For early power estimation when an AMD Vivado™ design is not yet available or ready.

  1. Manually specify the configuration of NoC data paths as described above to get the estimated power.
  2. Create a DDR interface using the DDRMC Wizard if you are using a hard DDRMC in your design.
Note: For fewer paths, number of clock buffers are average estimation per path. It is suggested to import clock buffers from Vivado whenever possible.

Importing from Vivado

If there is an IP integrator design available in Vivado with NoC present as an IP, use this flow for NoC power estimation. In this flow, Vivado generates the .xpe file with all the information required for NoC power estimation.

  1. In the Vivado IP integrator design, when validate_bd_design is run, the NOC_Power.xpe file is generated with all the NoC configurations.
  2. Once the .xpe file for NoC design is generated, import this .xpe file into the PDM tool using Import NoC .xpe button available on top of NoC/DDRMC page.

The power estimated by this flow is more accurate than the manual entry mode. In this flow, the NoC configuration is populated from the actual NoC design and the number of switches and clock buffers are very close to the numbers used in the design.