CPM - 2023.1 English

Power Design Manager User Guide (UG1556)

Document ID
UG1556
Release Date
2023-05-16
Version
2023.1 English

The Hard_Blocks page supports an independent subsystem called the CPM. The CPM contains a Type-A PCIe (Gen4 x16) controller and also the necessary hardened components to allow a fabric accelerator to act as a cache coherent interconnect for accelerator (CCIX). The CPM subsystem power is estimated based on the number of controllers used. PDM allows selection of PCIe configuration such as link, speed and width. The controller supports Gen1, Gen2, Gen3, Gen4 PCIe modes, up to x16 lanes. It also supports a CCIX only ESM mode (20 or 25 Gbps). PDM uses PCIe Core A0 by default for CPM and it supports fiver different modes for CPM based on CPM use models. These modes are as follows:

  • CCIX
  • CCIX_L2 - (L2 cache)
  • PCIE_Controller_Only
  • PCIE_Controller_DMA
  • PCIE_Controller_Bridge

PCIe® Core A1 does not support the DMA and Bridge mode.

Figure 1. Create Hard IP Wizard

Figure 2. CPM