AI Engine-ML - 2023.1 English

Power Design Manager User Guide (UG1556)

Document ID
UG1556
Release Date
2023-05-16
Version
2023.1 English

AI Engine-ML is available in Versal AI Edge and a few AI Core series devices. The compute tiles are similar to AI-Engine tiles with additional support for BFloat data type. AIE-ML has additional shared memory tiles for improved performance and data movement.

The maximum total supported memory by memory tile is up to 38 Mb across AI Engine Array, depending on the device. Memory tile memory banks have 512 KB SRAM, arranged in 16 physical banks, each 128-bit wide and 2K words deep. For early estimation, an average number of memory banks that can be used is computed and auto-populated by PDM.

AIE-ML supports import of .xpe file that is generated from Vitis AI Engine ML compiler, which is similar to AI Engine for more accurate usage and read/write rates.

For more information please refer to Versal Adaptive SoC AIE-ML Architecture Manual (AM020).

Figure 1. AI Engine-ML