Using the CLOCK_ROUTE_GUIDE Constraint - 2023.1 English

Versal Adaptive SoC Hardware, IP, and Platform Development Methodology Guide (UG1387)
Document ID
UG1387
Release Date
2023-05-24
Version
2023.1 English

The CLOCK_ROUTE_GUIDE is a STRING property that can be applied to clock pin objects. This property allows you to define the route a specified clock net is supposed to take to load a pin in the XPIO. Valid values are CMT_ROW, BUFDIV_LEAF, and ANY.

Note: This property only applies to the XPIO clock loads.

The following table summarizes the different CLOCK_ROUTE_GUIDE constraint values, use, and behavior.

Table 1. Versal Device CLOCK_ROUTE_GUIDE Constraint Summary
Value Use Behavior
CMT_ROW A horizontal route only contained in the XPIO clock region row

Example:

set_property CLOCK_ROUTE_GUIDE CMT_ROW [get_pins myHier/myBUFG/I]
 When CLOCK_ROUTE_GUIDE == CMT_ROW, the clock routing should be contained in the XPIO clock region row.
BUFDIV_LEAF When routing to use a BUFDIV_LEAF through BLI when reaching the XPIO

Example:

set_property CLOCK_ROUTE_GUIDE BUFDIV_LEAF [get_pins myHier/myBUFG/I]
 When CLOCK_ROUTE_GUIDE == BUFDIV_LEAF, the clock routing should go through the BUFDIV_LEAF and the BLI.
ANY When routing to use an ANY possible route when reaching the XPIO

Example:

set_property CLOCK_ROUTE_GUIDE ANY [get_pins myHier/myBUFG/I]
 When CLOCK_ROUTE_GUIDE == ANY, the clock routing can go through ANY permitted nodes.

When CLOCK_ROUTE_GUIDE == BUFDIV_LEAF, the clock routing should go through the BUFDIV_LEAF and the BLI.

When CLOCK_ROUTE_GUIDE == CMT_ROW, the clock routing should be contained in the HSR row.

Here is an example code for BUFDIV_LEAF:

set_property CLOCK_ROUTE_GUIDE BUFDIV_LEAF [get_pins sample_clk_mmcm/inst/clock_primitive_inst/MMCME5_inst/CLKFB1_DESKEW]

The figure below shows the clock routing going through the BUFDIV_LEAF and the BLI for the XPLL feedback path.

Figure 1. CLOCK_ROUTE_GUIDE Constraint Set to BUFDIV_LEAF

Here is an example code for CMT_ROW:

set_property CLOCK_ROUTE_GUIDE CMT_ROW [get_pins receiver_inst/xpll_fifo_wr_clk/CLKFB1_DESKEW]

The figure below shows the clock routing solely contained in the XPIO Bank for the MMCM feedback path.

Figure 2. CLOCK_ROUTE_GUIDE Constraint Set to CMT_ROW

To use the CLOCK_ROUTE_GUIDE, enter the constraint and assign the value depending on desired behavior. The current supported values are CMT_ROW, BUFDIV_LEAF, and ANY.

For example, when you want a horizontal route only contained in the XPIO bank where the clock management tiles are aligned in a row:

set_property CLOCK_ROUTE_GUIDE CMT_ROW [get_pins myHier/myBUFG/I]

For example, when you want the route to use a BUFDIV_LEAF through BLI when reaching the XPIO:

set_property CLOCK_ROUTE_GUIDE BUFDIV_LEAF [get_pins myHier/myBUFG/I]