The following table shows the revision history for this document.
| Section | Revision Summary |
|---|---|
| 05/24/2023 Version 2023.1 | |
| Document title | Changed title to Versal Adaptive SoC Hardware, IP, and Platform Development Methodology Guide (UG1387). |
| System Design Types | Added HBM. |
| Design Planning Considerations for the Traditional Design Flow | Added design flow figure. |
| Design Planning Considerations for the Platform-Based Design Flow | Added design flow figure. |
| Design Planning Considerations for Dynamic Function eXchange | Added design flow figure and BDC-based DFX design description. |
| Design Planning Considerations for DFX-based Vitis Acceleration Platform Development | Added DFX and non-DFX embedded platform creation description in platform setup. |
| Recommendations for Designing with Versal Device IP | Added AM017 reference. |
| Recommendations for Different Versal Device Design Topologies | Added CIPS and NoC description to BD design. |
| Design Creation with RTL | Added UG899 link and description. |
| Clock Primitives | Added AM017 reference. |
| Improving Fmax Guidance | Added section. |
| Low Fanout Clocks | Added BUFG_GTs description. |
| Using the CLOCK_ROUTE_GUIDE Constraint | Added section. |
| USER_CLOCK_ROOT Assignment | Added USER_CLOCK_ROOT clarification. |
| Synchronous CDC | Added CDC path input/output clocks note. |
| NoC Considerations | Added SSI technology description. |
| Designing with HBM Devices | Added chapter. |
| Incremental Synthesis | Updated to 50000 instances. |
| References | Added AM017 reference. |