Placement Analysis - 2023.1 English

Versal Adaptive SoC Hardware, IP, and Platform Development Methodology Guide (UG1387)

Document ID
UG1387
Release Date
2023-05-24
Version
2023.1 English

Use the timing summary report after placement to check the critical paths.

  • Paths with very large negative setup time slack may require that you check the constraints for completeness and correctness, or logic restructuring to achieve timing closure.
  • Paths with very large negative hold time slack are most likely due to incorrect constraints or bad clocking topologies and should be fixed before moving on to route design.
  • Paths with small negative hold time slack are likely to be fixed by the router. You can also run report_clock_utilization after place_design to view a report that breaks down clock resource and load counts by clock region.

For more information, see this link in the Versal Adaptive SoC System Integration and Validation Methodology Guide (UG1388). For more information on placement, see this link in the Vivado Design Suite User Guide: Implementation (UG904).