If there is not enough NoC bandwidth, consider pipelining for the modules farther from the HBM stacks. Occasionally the design contains many pipelines and it might be challenging for the tool to analyze SLR partitioning, use the SLR level floorplanning to optimize the HBM stacks. For SLR level floorplanning, evaluate where the logic is located based on connections to anchor points like PS, GT, IOs, and special/hard IPs. Consider floorplan alignment of the HBM stack and connectivity (for example, left stack should align on the left side connectivity and likewise for the right stack).
Tip: Avoid connecting the
same logic/modules to multiple stacks and avoid connectivity crisscrossing from left to
right.