Kernel Debug and Verification Considerations - 2023.1 English

Versal Adaptive SoC Hardware, IP, and Platform Development Methodology Guide (UG1387)

Document ID
UG1387
Release Date
2023-05-24
Version
2023.1 English

Following are recommendations when debugging and verifying kernels:

  • Verify RTL kernels in their own test bench using advanced verification techniques including verification components, randomization, and protocol checkers. The AXI Verification IP (VIP) is available in the Vivado IP catalog and can help with the verification of AXI interfaces. The RTL kernel example designs contain an AXI VIP-based test bench with sample stimulus files.
  • Use hardware emulation to test the host code software integration or to view the interaction between multiple kernels.

Verifying the RTL kernel with logic simulation is a block-level task. Verifying the RTL kernel with hardware emulation is a system integration task. For more information about the logic simulation and the hardware emulation flows for Versal adaptive SoC, see this link in the Versal Adaptive SoC System Integration and Validation Methodology Guide (UG1388).