The following table shows the breakdown of the s_axis interface signals.
| Name | I/O | Description |
|---|---|---|
| s_axis_tdata | I | Packet data bus of configurable width. |
| s_axis_tvalid | I | Indicates that the master is driving a valid transfer. A transfer takes place when both s_axis_tvalid and s_axis_tready are asserted. |
| s_axis_tkeep | I | Indicates whether the content of the associated byte of s_axis_tdata is processed as part of the data stream. Note: This value must be set to all 1s for all words of a packet except the TLAST word, where the valid bytes must be right-justified (no invalid byte gaps). The all 0s value is not currently supported on this input interface, except for a null packet length where there are no headers to be inserted into the packet. |
| s_axis_tlast | I | Indicates the boundary of the packet. |
| s_axis_tuser | I | User-defined sideband information transmitted alongside the data
stream. Only present if the axis_tuser
keyword appears as a field name within the user metadata
structure of a P4 program. It is only valid for the first word of an
incoming packet to the Vitis Networking P4 IP, validated by s_axis_tvalid. |
| s_axis_tdest | I | Provides routing information for the data stream. It is only present
if the axis_tdest keyword appears as a field
name within the user metadata structure of a P4 program. It is only
valid for the first word of an incoming packet to the Vitis
Networking P4 IP, validated by s_axis_tvalid. |
| s_axis_tid | I | Data stream identifier that indicates different streams of data. It is
only present if the axis_tid keyword appears
as a field name within the user metadata structure of a P4 program.
It is only valid for the first word of an incoming packet to the
Vitis Networking P4 IP, validated by s_axis_tvalid. |
| s_axis_tready | O | Indicates that the slave can accept a transfer in the current cycle. |
Packet Rate Limiter
There is an optional packet rate limiter at the input of the Vitis Networking P4 IP enforcing the specified packet rate (PKT_RATE) by de-asserting s_axis_tready when necessary. When enabled, the packet rate limiter (PRL) enforces the user-specified PKT_RATE by ensuring that the time from each Start of Packet (based on previous s_axis_tlast) does not exceed the PKT_RATE. s_axis_tready is de-asserted at the end of a packet (following the s_axis_tlast word) if a gap is required before the next packet. Specifically, the PRL uses the AXI Stream Clock Frequency to PKT_RATE ratio, rounded up to the nearest power of 2. The PRL is only used if a CAM exists in the design (excluding TinyBCAM/TinyTCAM) since all other parts of Vitis Networking P4 can cope with the maximum packet rate equal to the AXI-Stream clock frequency.
If the Packet Rate Limiter is not enabled, the s_axis_tready signal may still be de-asserted in cases where the PKT_RATE setting is exceeded, but this is not applied as strictly on a per-packet basis and it can depend on a number of factors within the design.
See Top Level Settings for details on how to enable the Packet Rate Limiter.