User Extern Interface - User Extern Interface - 2023.1 English - UG1308

The user extern interface provides a simple data and valid signal for input and output, synchronous to the s_axis_aclk domain. A single user extern waveform is shown in the following figure.

Figure 1. Single User Extern Waveform

These vector signals are extended in width to cover all user extern instances from the user’s P4 program (for example, a single valid bit per user extern instance). The generated SystemVerilog package file includes a set of constants and a structure definition to interpret the bit definition of these signals based on the P4 program names (see Generated Files more information). A waveform displaying two user externs is shown in the following figure.

Figure 2. Two User Externs Waveform

Vitis Networking P4 only supports fixed latency for the user Extern. For every packet that executes the apply method of a user Extern instance, there is a corresponding assertion of the user_extern_out_valid signal for one clock cycle. Then after a fixed number of clock cycles (as specified in the fixed_latency value of the User Extern instance in the P4 program), the corresponding bit of the user_extern_in_valid signal is expected to be asserted for one clock cycle.

There is no support for back-pressure signaling on this user Extern interface. Also note that the inter-packet gap might not be maintained from the S_AXIS interface to the user Extern interface. For example, it is possible to get back-to-back assertions on user_extern_out_valid even if the worst case is a new packet every two cycles on the S_AXIS interface. This is because of variable latency through the Parser.