The following are the reset signals used in the Vitis Networking P4 IP:
-
s_axis_aresetn: Active Low slave AXI4-Stream reset. -
s_axi_aresetn: Active Low AXI4-Lite reset. It resets the AXI4-Lite interface signaling but it does not reset any of the register maps (such as Statistics Registers and table entries). -
m_axi_hbm_aresetn: Active Low HBM reset. This is the DRAM memory interface reset. It resets all FSMs that manage memory access, pending and uncompleted memory transactions.